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CMX661 pair gain dual spm detector ? 2001 consumer microcircuits limited d/661/2 december 2001 provisional information features applications two (12khz/16khz) spm detectors pair - gain systems standard 3.579545mhz x tal out - of - band signalling systems selectable bandwidth limits excellent speech - band rejection call charge applications in pbx and pabx line cards low power 3.0v to 5.0v operation 1.1 brief description the CMX661 is a low power, dual subscriber pulse metering (spm) detector ? two detectors on a single chip ? to indicate the presence on a telephone line of either 12khz or 16khz telephone call charge frequencies. the detection frequency and bandwidth are common to both detectors and may be externally selected. the detection sen sitivity is set independently for each channel by external components and the detector outputs can be set to a high impedance state for device multiplexing requirements in pbx and pabx line card applications. flexibility of decode bandwidth settings allow s the CMX661 to operate in systems where the spm generation is not necessarily perfectly accurate or stable. external hardwired selection of functionality economises on the number of host c i/o control lines required, whilst the rapid response and de - res ponse times of the CMX661 permit flexible tone length qualification by the host c. the CMX661 offers low (3.0v) operating voltage and power, consuming ? 750a at 3v. it is available in low - cost 16 - pin plastic dil and soic packages.
pair gain dual spm detector CMX661 ? 2001 consumer microcircui ts limited 2 d/661/2 contents section page 1.0 features and applications ................................ ................................ .. 1 1.1 brief description ................................ ................................ .................. 1 1.2 block diagram ................................ ................................ ..................... 3 1.3 signal list ................................ ................................ ............................ 4 1.4 external components ................................ ................................ .......... 6 1.5 general description ................................ ................................ ............. 7 1.5.1 description of blocks ................................ ............................. 7 1.5.2 operating states ................................ ................................ ..... 7 1.6 application notes ................................ ................................ ................ 9 1.6.1 signal input configurations ................................ ................... 9 1.6.2 crystal/clock distribution ................................ ...................... 9 1.6.3 channel 1 and channel 2 output format .............................. 9 1.6.4 setting level sensitivity via e xternal components ............ 10 1.6.5 aliasing ................................ ................................ .................. 10 1.7 performance specification ................................ ................................ 12 1.7.1 electrical performance ................................ .......................... 12 1.7.2 packaging ................................ ................................ .............. 15
pair gain dual spm detector CMX661 ? 2001 consumer microcircui ts limited 3 d/661/2 1.2 block diagram figure 1 block diagram
pair gain dual spm detector CMX661 ? 2001 consumer microcircui ts limited 4 d/661/2 1.3 signal list package d4 package p3 signal description pin no. pin no. name type 1 1 xtal i/p the i nput of the on - chip oscillator for use with a 3.579545mhz xtal in conjunction with the xtaln output; circuit components are on - chip. 2 2 xtaln o/p the inverted output of the on - chip oscillator. 3 3 ch2 op o/p the digital output of the channel 2 spm detec tor, when enabled. logic '0' (low) when tone is detected. 4 4 ch1 op o/p the digital output of the channel 1 spm detector, when enabled. logic '0' (low) when tone is detected. 5 5 ch1 amp out o/p the output of the channel 1 input amplifier. see figures 2 and 3. 6 6 ch1 amp in ( - ) i/p the negative input to the channel 1 input amplifier. see figures 2 and 3. 7 7 ch1 amp in (+) i/p the positive input to the channel 1 input amplifier. see figures 2 and 3. 8 8 v ss power the negative supply rail (ground ). 9 9 ch2 amp in (+) i/p the positive input to the channel 2 input amplifier. see figures 2 and 3. 10 10 ch2 amp in ( - ) i/p the negative input to the channel 2 input amplifier. see figures 2 and 3. 11 11 ch2 amp out o/p the output of the channel 2 in put amplifier. see figures 2 and 3. 12 12 op enablen i/p for multi - chip output multiplexing; controls the state of both channel 1 and channel 2 outputs. when this input is placed high (logic ?1?) both outputs are set to a high impedance. when placed at l ogic '0' (low) both outputs are enabled. 13 13 d0 i/p the lsb of the two bits which set the 'will decode' bandwidth of the CMX661.
pair gain dual spm detector CMX661 ? 2001 consumer microcircui ts limited 5 d/661/2 package d4 package p3 signal description pin no. pin no. name type 14 14 d1 i/p the msb of the two bits which set the 'will decode' bandwidth of the CMX661. 15 15 system select i/p selects the system frequency. high (logic ?1?) = 12khz; low (logic ?0?) = 16khz. this signal has an internal pullup resistor, so if left unconnected the CMX661 will detect 12khz by d efault. 16 16 v dd power the positive supply rail. critical levels and voltages within the CMX661 are dependent upon this supply. this pin should be decoupled to v ss by a capacitor mounted close to the device pins. notes: i/p = input o/p = output bi = bidirectional
pair gain dual spm detector CMX661 ? 2001 consumer microcircui ts limited 6 d/661/2 1.4 external components figure 2 typical external components r1 120k w 1% r7 100k w 1% c1 1.0f 20% r2 120k w 1% r8 100k w 1% c2 1.0f 20% r3 100k w 1% r9 15k w 1% c3 330pf 5% r4 100k w 1% r10 15k w 1% c4 330pf 5% r5 120k w 1% c5 330pf 5% r6 120k w 1% x1 3.579545mhz c6 330pf 5% input amplifier components r1, c3, r2, c4, r5, c5, r6 and c6 should be chosen to set the required sensitivity of the CMX661 (see section 1.6.4). typical values only are shown above. note that when calculating/selecting gain components, r3, r4, r7 and r8 should always be greater than or equal to 100k w . v bias is not available from the CMX661 and so must be generated by an external voltage divider (r9 and r10) from v dd . particular attention should be paid to decoupling v dd and keeping the power, ground and signal lines free from unnecessary noise. telephone systems may have unusually high dc and ac voltages present on the line, as either different ial or common mode signals. if the CMX661 is part of a host system which does not have its own input protection, then protection diodes must be added to both signal inputs (+ and ) so that the voltage on any pin is limited to within v ss 0.3v and v dd + 0.3v. the breakdown voltage of capacitors and the peak inverse voltage of diodes must be sufficient to withstand the sum of the dc and peak - peak ac voltages applied.
pair gain dual spm detector CMX661 ? 2001 consumer microcircui ts limited 7 d/661/2 1.5 general description 1.5.1 description of blocks crystal oscillator and clock dividers these circuits derive the internal logic clocks, decode frequencies and transmit frequencies by frequency division of a reference frequency which is generated by the on - chip crystal oscillator. the only external component required is a 3.579545mhz crystal, which should be connected across the xtal and xtaln pins . all other oscillator components are on - chip. input operational amplifiers the input signals are applied to the CMX661 via these amplifiers, which use the external components shown in figure 2. the external gain setting components should be calculated by the method described in section 1.6.4, using the values obtained from figure 5. spm tone bandpass filter these are tone bandpass/audio reject filters automatically centred on the system frequency (12khz or 16khz) being detected. their gain is constant so the internal device sensitivity is also constant. level detection and pulse generator circuits the outputs from the bandpass filters are input to these circuits which perform the signal level discrimination function for the CMX661. signals which fulfil the system level req uirements cause a stream of digital pulses, one per 32 cycles of input signal, to be generated. these pulses are sent to the period measurement circuitry. period measurement logic this digital circuit block inputs the stream of pulses from the level de tection circuits and measures their repetition rate against a predetermined maximum and minimum. because each pulse from the level detect circuit occurs once per 32 cycles of input signal, this has the effect of averaging the input signal period over this number of cycles. a valid spm tone is recognised when 3 successive correctly spaced pulses are received. this causes a signal to appear immediately at the relevant channel output signifying receipt of a valid spm signal. depending upon the frequency, wi thin the legal bandwidth, received, the CMX661 should respond within 10 - 15ms (see section 1.7 and figure 4). output enable circuits these enable the output logic pins ?channel 1 output? and ?channel 2 output?. these outputs can be made high impedance by setting the op enablen pin high. when enabled, a high (logic ?1?) indicates the tone is absent, a low (logic ?0?) indicates the tone is present. 1.5.2 operating states the CMX661 is a dual - channel spm detector where both detectors are set to the same bandwidth and system frequency (12khz or 16khz). the sensitivity of each detector is set via external components. the decode bandwidths can be set to 1.5%, 3%, 5% and 7.5% of the nominal tone frequency by mean s of the d0 and d1 logic inputs and the system frequency is set by the system select logic input. each decoder logic output has a very short response and deresponse time so that it forms an ?envelope? of the input tone. host c systems must decide whethe r the received signal fulfils the system tone pulse length requirements. the outputs can be set to a high impedance state for device multiplexing by use of the op enablen pin (logic '1' gives a high impedance state on the decoder outputs, logic '0' gives a normal (logic) output on these pins). the sensitivity of each channel is set by correct selection of external components around each channel input amplifier. see section 1.6.4 and figure 5 for a method of selecting amplifier gain and components to meet a particular sensitivity requirement.
pair gain dual spm detector CMX661 ? 2001 consumer microcircui ts limited 8 d/661/2 will detect and will not detect bandwidths there are four selectable bandwidths which are common to both channels. the ?will detect? bandwidth can be programmed to 1.5%, 3%, 5% or 7.5%. the corresponding ?will not detect? band edges are 4%, 5.5%, 7.5% and 10%. pins d0 and d1 program the bandwidth selection, shared by both channels, as shown in tables 4 and 5. d0 - d1 (both channels) lower will not detect lower will detect upper will detect upper will not de tect 00 11.52khz ( - 4.0%) 11.82khz ( - 1.5%) 12.18khz (+1.5%) 12.48khz (+4.0%) 01 11.34khz ( - 5.5%) 11.64khz ( - 3.0%) 12.36khz (+3.0%) 12.66khz (+5.5%) 10 11.10khz ( - 7.5%) 11.40khz ( - 5.0%) 12.60khz (+5.0%) 12.90khz (+7.5%) 11 10.80khz ( - 10.0%) 11.10khz ( - 7. 5%) 12.90khz (+7.5%) 13.20khz (+10.0%) table 4 setting 12khz will detect/will not detect bandwidths d0 - d1 (both channels) lower will not detect lower will detect upper will detect upper will not detect 00 15.36khz ( - 4.0%) 15.76khz ( - 1.5%) 16.24khz (+1 .5%) 16.64khz (+4.0%) 01 15.12khz ( - 5.5%) 15.52khz ( - 3.0%) 16.48khz (+3.0%) 16.88khz (+5.5%) 10 14.80khz ( - 7.5%) 15.20khz ( - 5.0%) 16.80khz (+5.0%) 17.20khz (+7.5%) 11 14.40khz ( - 10.0%) 14.80khz ( - 7.5%) 17.20khz (+7.5%) 17.60khz (+10.0%) table 5 setti ng 16khz will detect/will not detect bandwidths the CMX661 will always respond to valid inputs between the lower ?will detect? and upper ?will detect? frequencies inclusive. it will not respond to frequencies at or below the lower ?will not detect? or at or above the upper ?will not detect?. system select the system select pin selects the operating frequencies of the CMX661 (logic '1' = 12khz, logic '0' = 16khz).
pair gain dual spm detector CMX661 ? 2001 consumer microcircui ts limited 9 d/661/2 1.6 application notes 1.6.1 signal input confi gurations figure 3 shows how the input amplifiers can be connected as differential mode or common mode amplifiers, according to the application. figure 3 example input configurations external com ponents are necessary to generate the bias voltage for the input op - amps. (the voltage labelled v bias in figure 3). this could be a potential divider consisting of two 15k w resistors and a 1.0f capacitor to decouple the output. 1.6.2 crystal/clock dist ribution the CMX661 requires a 3.579545mhz crystal. with the exception of the crystal, all oscillator components are incorporated on chip. 1.6.3 channel 1 and channel 2 output format figure 4 illustrates the output format, which is the same for both channels. figure 4 detector output format
pair gain dual spm detector CMX661 ? 2001 consumer microcircui ts limited 10 d/661/2 1.6.4 setting level sensitivity via external components the sensitivities of the two channels are set by the correct selection of the components around the channel input amplifiers. input gain calculation: the input amplifiers, with their external circuitry, are av ailable to set the sensitivity of the CMX661 to conform to the user?s national level specification with regard to ?must? and ?must - not? decode signal levels. with reference to the graph in figure 5, the following steps will assist in the determination of the required gain/attenuation. step 1 draw two horizontal lines from the y - axis {signal level db(ref)} the upper line will represent the required ?must? decode level the lower line will represent the required ?must - not? decode level. step 2 mark the int ersection of the upper horizontal line and the upper sloping line; drop a vertical line from this point to the x - axis {amplifier gain (db)}. the point where the vertical line meets the x - axis will indicate the minimum input gain required for reliable deco ding of valid signals. step 3 mark the intersection of the lower horizontal line and the lower sloping line; drop a vertical line from this point to the x - axis. the point where the vertical line meets the x - axis will indicate the maximum allowable input amp gain. input signals at or below the ?must - not? decode level will not be detected as long as the amplifier gain is no higher than this level. step 4 refer to the gain components shown in figure 2. the user should calculate and select external compon ents (r1/r3/c3, r2/r4/c4 and r5/r7/c5, r6/r8/c6) to provide amplifier gains within the limits obtained in steps 2 and 3. component tolerances should not move the gain figure outside these limits. resistors r3, r4, r7 and r8 should always be greater than or equal to 100k w . it is recommended that the designed gain is near the centre of the calculated range. note that the device sensitivity is directly proportional to the applied power supply (v dd ). the graph in figure 5 is for the calculation of input ga in components for the CMX661 using a v dd of 5.0 (0.1) volts. subtract 4.44db from the amplifier gain for operation at 3.0v volts. 1.6.5 aliasing due to the switched - capacitor filters employed in the CMX661, care should be taken to avoid any aliasing effects by removing all frequencies above 579.390khz (16khz mode) or 434.543khz (12khz mode). this can be achieved by adding bypass capacitors across r3, r4, r7 and r8, setting the - 3db breakpoint of each resistor - capacitor combination such that there is sufficient attenuation at the alias frequency and negligible effect at the desired spm frequency.
pair gain dual spm detector CMX661 ? 2001 consumer microcircui ts limited 11 d/661/2 figure 5 input gain calculation graph
pair gain dual spm detector CMX661 ? 2001 consumer microcircui ts limited 12 d/661/2 1.7 performance specification 1.7.1 electrical performance 1.7.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. units supply (v dd - v ss ) - 0.3 7.0 v voltage on any pin t o v ss - 0.3 v dd + 0.3 v current into or out of v dd and v ss pins - 30 +30 ma current into or out of any other pin - 20 +20 ma d4/p3 package min. max. units total allowable power dissipation at tamb = 25c 800 mw ... derating 13 mw/c s torage temperature - 55 +125 c operating temperature - 40 +85 c 1.7.1.2 operating limits correct operation of the device outside these limits is not implied. notes min. max. units supply (v dd - v ss ) 2.7 5.5 v operating temperature - 40 +85 c xtal frequency 3.558918 3.589368 mhz
pair gain dual spm detector CMX661 ? 2001 consumer microcircui ts limited 13 d/661/2 1.7.1.3 operating characteristics for the following conditions unless otherwise specified: xtal frequency = 3.579545mhz, audio level 0db(ref) = 775vrms. noise bandwidth = 50khz, v dd = 3.0v to 5.5v, tam b = - 40c to +85c. system setting = 12khz or 16khz. notes min. typ. max. units dc parameters i dd 1 1.25 2.5 ma i dd 2 0.75 1.5 ma logic inputs input logic ?1? level 80% v dd input logic ?0? level 20% v dd input leakage current (vin = 0 to v dd ) 3 - 5.0 +5.0 a input capacitance 7.5 pf input current (vin =0) 4 - 15.0 a channel outputs output logic ?1? level (1 oh = 120a) (enabled) 90% v dd output logic ?0? level (1 ol = 360a) (enabled) 10% v dd off state leakage current (high z output) - 5.0 5.0 a mode change time 5 500 ns response and de - response time 6, 7, 8 15.0 ms input amplifiers input impedance (at 100hz) 10.0 m w open loop voltage gain (1mvrms i/p at 100hz) 500 v/v common mode range 10% 90% v dd input signal level 100% v dd output impedance (open loop) 6.0 k w overall performance 12khz detect bandwidth 6, 9 11.82 12.18 khz 1 2khz detect bandwidth 6, 10 11.64 12.36 khz 12khz detect bandwidth 6, 11 11.40 12.60 khz 12khz detect bandwidth 6, 12 11.10 12.90 khz 12khz not detect frequencies (below 12khz) 6, 9 11.52 khz 12khz not detect frequencies (below 12khz) 6, 10 11.34 khz 12khz not detect frequencies (below 12khz) 6, 11 11.10 khz 12khz not detect frequencies (below 12khz) 6, 12 10.80 khz 12khz not detect frequencies (above 12khz) 6, 9 12.48 khz 12khz not detect frequencies (above 12khz) 6, 10 12.66 khz 12khz not detect frequencies (above12khz) 6, 11 12.90 khz 12khz not detect frequencies (above12khz) 6, 12 13.20 khz 16khz detect bandwidth 6, 9 15.76 16.24 khz 16khz detect bandwidth 6, 10 15.52 1 6.48 khz
pair gain dual spm detector CMX661 ? 2001 consumer microcircui ts limited 14 d/661/2 1.7.1.3 operating characteristics (continued) notes min. typ. max. units 16khz detect bandwidth 6, 11 15.20 16.80 khz 16khz detect bandwidth 6, 12 14.80 17.20 khz 16khz not - detect frequencies (below 16khz) 6, 9 15.36 khz 1 6khz not - detect frequencies (below 16khz) 6, 10 15.12 khz 16khz not - detect frequencies (below 16khz) 6, 11 14.80 khz 16khz not detect frequencies (below 16khz) 6, 12 14.40 khz 16khz not - detect frequencies (above 16khz) 6, 9 16.64 k hz 16khz not - detect frequencies (above 16khz) 6, 10 16.88 khz 16khz not - detect frequencies (above 16khz) 6, 11 17.20 khz 16khz not - detect frequencies (above 16khz) 6, 12 17.60 khz level sensitivity level sensitivity is set by external components (see figure 2) 6, 7, 13 - 25 - 26.7 - 28.5 db signal quality requirements for correct operation (see figure 2) signal to noise ratio (amp input) 7, 14, 15, 16 22.0 20.0 db signal to voice ratio (amp input) 7, 14, 15, 17 - 36. 0 - 40.0 db signal to voice ratio (amp output) 7, 14, 16, 17 - 25.0 - 27.0 - 29.0 db notes: 1. at 5.0v. not including any current drawn from the pins by external circuitry. 2. at 3.0v. not including any current drawn from the pins by external circuit ry. 3. logic pins with no internal pullup or pulldown resistors: op enablen, d0 and d1. 4. logic pins with an internal pullup or pulldown resistor: system select. 5. time taken to change between high impedance and operating modes, with a maximum capacitive load of 30pf on an output. 6. with adherence to signal to voice and signal to noise specifications. 7. 12khz and/or 16khz system. 8. the time delay after device powerup, change of bandwidth setting or change in input signal conditions, before the condition of the outputs c an be guaranteed correct. 9. with ?will detect? bandwidth set to 1.5%. 10. with ?will detect? bandwidth set to 3.0%. 11. with ?will detect? bandwidth set to 5.0%. 12. with ?will detect? bandwidth set to 7.5%. 13. with input amplifier gain setting of 0db via external comp onents and measured at amplifier output with v dd =5.0v. signal sensitivity is proportional to v dd . 14. for immunity to false responses and/or deresponses. 15. common mode spm and balanced voice signal. 16. with balanced spm and voice signals. to avoid false derespon ses due to saturation, the peak to peak voice + noise level at the output of the input amplifier should be no greater than the dynamic range of the device. 17. maximum voice frequencies = 3.4khz.
pair gain dual spm detector CMX661 ? 2001 consumer microcircui ts limited 15 d/661/2 1.7.2 packaging figu re 6 d4 mechanical outline: order as part no. CMX661d4 figure 7 p3 mechanical outline: order as part no. CMX661p3
pair gain dual spm detector CMX661 handling precautions: this product inclu des input protection, however, precautions should be taken to prevent device damage from electro - static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circuit patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. specific testing of all circuit parameters is not necessarily performed. oval park - langford maldon - essex cm9 6wg - england telephone: +44 (0)1621 875500 telefax: +44 (0)1621 875600 e - mail: sales@cmlmicro.co.uk http://www.cmlmicro.co.uk

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